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Converting Flip-Flop to Clock-Gated 3-Phase Latch-Based Designs Using Graph-Based Retiming.

Huimei ChengXi LiYichen GuPeter A. Beerel
Published in: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. (2022)
Keyphrases
  • flip flops
  • power consumption
  • power dissipation
  • multiple input
  • single phase
  • master slave
  • high speed
  • graph model
  • low power
  • real time
  • neural network
  • cmos technology