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Chaeryung Park
Publication Activity (10 Years)
Years Active: 1993-2000
Publications (10 Years): 0
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Publications
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Chaeryung Park
,
Taewhan Kim
,
C. L. Liu
An Integrated Approach to Data Path Synthesis for Behavioral-level Power Optimization.
VLSI Design
2000 (4) (2000)
Chaeryung Park
,
Taewhan Park
,
C. L. Liu
An efficient data path synthesis algorithm for behavioral-level power optimization.
ISCAS (1)
(1999)
Chaeryung Park
,
Taewhan Kim
,
C. L. Liu
Register Allocation - A Hierarchical Reduction Approach.
J. VLSI Signal Process.
19 (3) (1998)
Chaeryung Park
,
Taewhan Kim
,
C. L. Liu
Register allocation for data flow graphs with conditional branches and loops.
EURO-DAC
(1993)