Srilata Raman

Publication Activity (10 Years)

Years Active: 1989-1997
Publications (10 Years): 0

Publications

Srilata Raman, Lalit M. Patnaik
Optimization Via Evolutionary Processes. Adv. Comput. 45 (1997)
Mohankumar Guruswamy, Robert L. Maziasz, Daniel Dulitz, Srilata Raman, Venkat Chiluvuri, Andrea Fernandez, Larry G. Jones
CELLERITY: A Fully Automatic Layout Synthesis System for Standard Cell Libraries. DAC (1997)
Srilata Raman, C. L. Liu, Larry G. Jones
Timing-Constrained FPGA Placement: A Force-Directed Formulation and Its Performance Evaluation. VLSI Design 4 (4) (1996)
Srilata Raman, C. L. Liu, Larry G. Jones
A Timing-Constrained Incremental Routing Algorithm for Symmetrical FPGAs. ED&TC (1996)
Srilata Raman, Lalit M. Patnaik
Performance-driven MCM partitioning through an adaptive genetic algorithm. IEEE Trans. Very Large Scale Integr. Syst. 4 (4) (1996)
Ananta K. Majhi, Lalit M. Patnaik, Srilata Raman
A genetic algorithm-based circuit partitioner for MCMs. Microprocess. Microprogramming 41 (1) (1995)
Srilata Raman, C. L. Liu, Larry G. Jones
A delay driven FPGA placement algorithm. EURO-DAC (1994)
Rajib Mall, Srilata Raman, Lalit M. Patnaik
A Parallel Simulated Annealing-Based Channel Router. Int. J. High Speed Comput. 6 (1) (1994)
Srilata Raman, Benjamin W. Wah
Quality-time tradeoffs in simulated annealing for VLSI placement. COMPSAC (1991)
Srilata Raman, Lalit M. Patnaik, Rajib Mall
Parallel Implementation of Circuit Simulation. Int. J. High Speed Comput. 2 (4) (1990)
Srilata Raman, Lalit M. Patnaik
An Annealing-Based Circuit Partitioner for Hypercube Architecture: Design and Performance Evaluation. Int. J. High Speed Comput. 2 (1) (1990)
Srilata Raman, Lalit M. Patnaik
Hirecs: Hypercube Implementation of Relaxation-Based Circuit Simulation. Int. J. High Speed Comput. 1 (3) (1989)