Noise-aware power optimization for on-chip interconnect.
Ki-Wook KimSeong-Ook JungUnni NarayananC. L. LiuSung-Mo KangPublished in: ISLPED (2000)
Keyphrases
- high speed
- power dissipation
- power consumption
- optimization process
- low cost
- signal to noise ratio
- global optimization
- optimization method
- missing data
- power distribution
- chip design
- ibm power processor
- noise reduction
- random noise
- noisy data
- input output
- median filter
- finite state machines
- gaussian noise
- additive noise
- power transmission