Shao-Yun Fang

Publication Activity (10 Years)

Years Active: 2010-2023
Publications (10 Years): 59

Top Topics

Design Methodologies

Optical Networks

Active Learning

Importance Sampling

Top Venues

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.

Publications

Kuei-Lin Wu, Shao-Yun Fang
Lamellar DSA-aware Detailed Routing Considering Double Patterning and Short Template Minimization. DAC (2023)
Yun-Jhe Jiang, Shao-Yun Fang
COALA: Concurrently Assigning Wire Segments to Layers for 2-D Global Routing. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 42 (2) (2023)
Yi-Sian Ciou, An-Jie Shih, Shao-Yun Fang, Yi-Yu Liu
Enhanced and Efficient Guiding Template Design for Lamellar DSA With Graph Monomorphism. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 42 (11) (2023)
Da-Wei Huang, Ying-Jie Jiang, Shao-Yun Fang
Spacing Cost-aware Optimal and Efficient Mixed-Cell-Height Detailed Placement for DFM Considerations. ICCAD (2023)
Hao-Chiang Shao, Hsing-Lei Ping, Kuo-Shiuan Chen, Weng-Tai Su, Chia-Wen Lin, Shao-Yun Fang, Pin-Yian Tsai, Yan-Hsiu Liu
Keeping Deep Lithography Simulators Updated: Global-Local Shape-Based Novelty Detection and Active Learning. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 42 (3) (2023)
Hung-Chun Lin, Shao-Yun Fang
MIA-Aware Detailed Placement and VT Reassignment for Leakage Power Optimization. ASP-DAC (2023)
Shao-Yun Fang
Advanced Design Methodologies for Directed Self-Assembly. ISPD (2023)
Hao-Chiang Shao, Chia-Wen Lin, Shao-Yun Fang
Data-Driven Approaches for Process Simulation and Optical Proximity Correction. ASP-DAC (2023)
Yun-Jhe Jiang, Shao-Yun Fang
Pin Access-Oriented Concurrent Detailed Routing. ISPD (2023)
Li-Chen Wang, Shao-Yun Fang
Mitigating Layout Dependent Effect-induced Timing Risk in Multi-Row-Height Detailed Placement. DATE (2023)
Sudip Poddar, Sukanta Bhattacharjee, Shao-Yun Fang, Tsung-Yi Ho, Bhargab B. Bhattacharya
Demand-Driven Multi-Target Sample Preparation on Resource-Constrained Digital Microfluidic Biochips. ACM Trans. Design Autom. Electr. Syst. 27 (1) (2022)
Bing-Yue Wu, Shao-Yun Fang, Hsiang-Wen Chang, Peter Wei
SpeedER: A Supervised Encoder-Decoder Driven Engine for Effective Resistance Estimation of Power Delivery Networks. MLCAD (2022)
Tsou-An Wu, Yun-Jhe Jiang, Shao-Yun Fang
A Robust Quantum Layout Synthesis Algorithm with a Qubit Mapping Checker. ICCAD (2022)
Hao-Chiang Shao, Hsing-Lei Ping, Kuo-shiuan Chen, Weng-Tai Su, Chia-Wen Lin, Shao-Yun Fang, Pin-Yian Tsai, Yan-Hsiu Liu
Keeping Deep Lithography Simulators Updated: Global-Local Shape-Based Novelty Detection and Active Learning. CoRR (2022)
Tao-Chun Yu, Shao-Yun Fang, Hsien-Shih Chiu, Kai-Shun Hu, Philip Hui-Yuh Tai, Cindy Chin-Fang Shen, Henry Sheng
Pin Accessibility Prediction and Optimization With Deep-Learning-Based Pin Pattern Recognition. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 40 (11) (2021)
Tao-Chun Yu, Shao-Yun Fang, Hsien-Shih Chiu, Kai-Shun Hu, Chin-Hsiung Hsu, Philip Hui-Yuh Tai, Cindy Chin-Fang Shen
Machine Learning-based Structural Pre-route Insertability Prediction and Improvement with Guided Backpropagation. ASP-DAC (2021)
Jia-Hong Chang, Shao-Yun Fang
Placement-guided pin layout substitution for routability optimization. Microelectron. J. 114 (2021)
Hao-Chiang Shao, Chao-Yi Peng, Jun-Rei Wu, Chia-Wen Lin, Shao-Yun Fang, Pin-Yen Tsai, Yan-Hsiu Liu
From IC Layout to Die Photograph: A CNN-Based Data-Driven Approach. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 40 (5) (2021)
Yun-Jhe Jiang, Kuo-Hao Wu, Shao-Yun Fang
Manufacturability Enhancement With Dummy via Insertion for DSA-MP Lithography Using Multiple BCP Materials. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 40 (2) (2021)
Yu-Kai Chuang, Yong Zhong, Yi-Hao Cheng, Bo-Yi Yu, Shao-Yun Fang, Bing Li, Ulf Schlichtmann
RobustONoC: Fault-Tolerant Optical Networks-on-Chip with Path Backup and Signal Reflection. ISQED (2021)
An-Jie Shih, Shao-Yun Fang, Yi-Yu Liu
Guiding Template Design for Lamellar DSA with Multiple Patterning and Self-Aligned Via Process. ICCAD (2020)
Yun-Jhe Jiang, Shao-Yun Fang
COALA: Concurrently Assigning Wire Segments to Layers for 2D Global Routing. ICCAD (2020)
Zhiyao Xie, Guan-Qi Fang, Yu-Hung Huang, Haoxing Ren, Yanqing Zhang, Brucek Khailany, Shao-Yun Fang, Jiang Hu, Yiran Chen, Erick Carvajal Barboza
FIST: A Feature-Importance Sampling and Tree-Based Method for Automatic Design Flow Parameter Tuning. CoRR (2020)
Yi-Hao Cheng, Tao-Chun Yu, Shao-Yun Fang
Obstacle-Avoiding Length-Matching Bus Routing Considering Nonuniform Track Resources. IEEE Trans. Very Large Scale Integr. Syst. 28 (8) (2020)
Tao-Chun Yu, Shao-Yun Fang, Hsien-Shih Chiu, Kai-Shun Hu, Philip Hui-Yuh Tai, Cindy Chin-Fang Shen, Henry Sheng
Lookahead Placement Optimization with Cell Library-based Pin Accessibility Prediction via Active Learning. ISPD (2020)
Kai-Chuan Yang, Tao-Chun Yu, Shao-Yun Fang, Teng-Yuan Cheng, Yang-Chun Liu, Cindy Chin-Fang Shen
Meshed Stack Via Design Considering Complicated Design Rules with Automatic Constraint Generation. ICCAD (2020)
Yong Zhong, Tao-Chun Yu, Kai-Chuan Yang, Shao-Yun Fang
Via Pillar-aware Detailed Placement. ISPD (2020)
Chih-Hsiang Hsu, Shao-Yun Fang
Stitch-Aware Routing Considering Smart Boundary for Multiple E-Beam Lithography. VLSI-DAT (2020)
Guan-Qi Fang, Yong Zhong, Yi-Hao Cheng, Shao-Yun Fang
Obstacle-Avoiding Open-Net Connector With Precise Shortest Distance Estimation. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 39 (5) (2020)
Zhiyao Xie, Guan-Qi Fang, Yu-Hung Huang, Haoxing Ren, Yanqing Zhang, Brucek Khailany, Shao-Yun Fang, Jiang Hu, Yiran Chen, Erick Carvajal Barboza
FIST: A Feature-Importance Sampling and Tree-Based Method for Automatic Design Flow Parameter Tuning. ASP-DAC (2020)
Hao-Chiang Shao, Chao-Yi Peng, Jun-Rei Wu, Chia-Wen Lin, Shao-Yun Fang, Pin-Yen Tsai, Yan-Hsiu Liu
From IC Layout to Die Photo: A CNN-Based Data-Driven Approach. CoRR (2020)
Yu-Hung Huang, Zhiyao Xie, Guan-Qi Fang, Tao-Chun Yu, Haoxing Ren, Shao-Yun Fang, Yiran Chen, Jiang Hu
Routability-Driven Macro Placement with Embedded CNN-Based Prediction Model. DATE (2019)
Chun-Wei Ho, Shao-Yun Fang
Capacitance Minimization Clock Synthesis with Blockage-Avoiding Hybrid-Structure Network. ISPACS (2019)
Tao-Chun Yu, An-Jie Shih, Shao-Yun Fang
Flip-Chip Routing With I/O Planning Considering Practical Pad Assignment Constraints. IEEE Trans. Very Large Scale Integr. Syst. 27 (8) (2019)
Bo-Yi Yu, Yong Zhong, Shao-Yun Fang, Hung-Fei Kuo
Deep learning-based framework for comprehensive mask optimization. ASP-DAC (2019)
Kuan-Jung Chen, Shao-Yun Fang
Printability Enhancement with Color Balancing for Multiple Patterning Lithography. IEEE Trans. Emerg. Top. Comput. 7 (2) (2019)
Tao-Chun Yu, Shao-Yun Fang, Hsien-Shih Chiu, Kai-Shun Hu, Philip Hui-Yuh Tai, Cindy Chin-Fang Shen, Henry Sheng
Pin Accessibility Prediction and Optimization with Deep Learning-based Pin Pattern Recognition. DAC (2019)
Zhi-Wen Lin, Shao-Yun Fang, Yao-Wen Chang, Wei-Cheng Rao, Chieh-Hsiung Kuan
-Neighbor-TSP-Based Subfield Scheduling for Electron-Beam Photomask Fabrication. IEEE Trans. Very Large Scale Integr. Syst. 26 (2) (2018)
Tao-Chun Yu, Shao-Yun Fang, Chia-Ching Chen, Yulong Sun, Poki Chen
Device Array Layout Synthesis With Nonlinear Gradient Compensation for a High-Accuracy Current-Steering DAC. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 37 (4) (2018)
Guan-Qi Fang, Yong Zhong, Yi-Hao Cheng, Shao-Yun Fang
Obstacle-avoiding open-net connector with precise shortest distance estimation. DAC (2018)
Shao-Yun Fang, Kuo-Hao Wu
Guiding Template-Induced Design Challenges in DSA-MP Lithography. ISVLSI (2018)
Yu-Kai Chuang, Kuan-Jung Chen, Kun-Lin Lin, Shao-Yun Fang, Bing Li, Ulf Schlichtmann
PlanarONoC: concurrent placement and routing considering crossing minimization for optical networks-on-chip. DAC (2018)
Tao-Chun Yu, Shao-Yun Fang
Flip-chip routing with IO planning considering practical pad assignment constraints. ASP-DAC (2018)
Zhiyao Xie, Yu-Hung Huang, Guan-Qi Fang, Haoxing Ren, Shao-Yun Fang, Yiran Chen, Nvidia Corporation
RouteNet: routability prediction for mixed-size designs using convolutional neural network. ICCAD (2018)
Hua-Yi Wu, Shao-Yun Fang
Triple patterning lithography-aware detailed routing ensuring via layer decomposability. VLSI-DAT (2018)
Kun-Lin Lin, Shao-Yun Fang, Yun-Xiang Hong
Design Optimization Considering Guiding Template Feasibility and Redundant Via Insertion for Directed Self-Assembly. IEEE Trans. Circuits Syst. I Regul. Pap. (12) (2017)
Kuo-Hao Wu, Shao-Yun Fang
Simultaneous template assignment and layout decomposition using multiple bcp materials in DSA-MP lithography. ICCAD (2017)
Kun-Lin Lin, Shao-Yun Fang
Guiding template-aware routing considering redundant via insertion for directed self-assembly. ASP-DAC (2017)
Kuan-Jung Chen, Yu-Kai Chuang, Bo-Yi Yu, Shao-Yun Fang
Minimizing Cluster Number with Clip Shifting in Hotspot Pattern Classification. DAC (2017)
Shao-Yun Fang, Yun-Xiang Hong, Yi-Zhen Lu
Simultaneous Guiding Template Optimization and Redundant via Insertion for Directed Self-Assembly. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 36 (1) (2017)
Shao-Yun Fang, Kuo-Hao Wu
Cut Mask Optimization With Wire Planning in Self-Aligned Multiple Patterning Full-Chip Routing. IEEE Trans. Very Large Scale Integr. Syst. 25 (2) (2017)
Shao-Yun Fang, Yun-Xiang Hong
Design optimization considering guiding template feasibility and redundant via insertion for directed self-assembly. APCCAS (2016)
Iou-Jen Liu, Shao-Yun Fang, Yao-Wen Chang
Overlay-Aware Detailed Routing for Self-Aligned Double Patterning Lithography Using the Cut Process. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 35 (9) (2016)
Iou-Jen Liu, Shao-Yun Fang, Yao-Wen Chang
Stitch-Aware Routing for Multiple E-Beam Lithography. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 34 (3) (2015)
Shao-Yun Fang, Yun-Xiang Hong, Yi-Zhen Lu
Simultaneous Guiding Template Optimization and Redundant Via Insertion for Directed Self-Assembly. ICCAD (2015)
Yao-Wen Chang, Ru-Gun Liu, Shao-Yun Fang
EUV and e-beam manufacturability: challenges and solutions. DAC (2015)
Shao-Yun Fang, Yi-Shu Tai, Yao-Wen Chang
Layout decomposition for Spacer-is-Metal (SIM) self-aligned double patterning. ASP-DAC (2015)
Zhi-Wen Lin, Shao-Yun Fang, Yao-Wen Chang, Wei-Cheng Rao, Chieh-Hsiung Kuan
Provably Good Max-Min-m-neighbor-TSP-Based Subfield Scheduling for Electron-Beam Photomask Fabrication. ICCAD (2015)
Shao-Yun Fang
Cut mask optimization with wire planning in self-aligned multiple patterning full-chip routing. ASP-DAC (2015)
Shao-Yun Fang, Yao-Wen Chang, Wei-Yu Chen
A Novel Layout Decomposition Algorithm for Triple Patterning Lithography. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 33 (3) (2014)
Iou-Jen Liu, Shao-Yun Fang, Yao-Wen Chang
Overlay-Aware Detailed Routing for Self-Aligned Double Patterning Lithography Using the Cut Process. DAC (2014)
Shao-Yun Fang, Iou-Jen Liu, Yao-Wen Chang
Stitch-aware routing for multiple e-beam lithography. DAC (2013)
Shao-Yun Fang, Wei-Yu Chen, Yao-Wen Chang
Graph-Based Subfield Scheduling for Electron-Beam Photomask Fabrication. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 32 (2) (2013)
Shao-Yun Fang, Chung-Wei Lin, Guang-Wan Liao, Yao-Wen Chang
Simultaneous OPC- and CMP-aware routing based on accurate closed-form modeling. ISPD (2013)
Shao-Yun Fang, Szu-Yu Chen, Yao-Wen Chang
Native-Conflict and Stitch-Aware Wire Perturbation for Double Patterning Technology. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 31 (5) (2012)
Shao-Yun Fang, Wei-Yu Chen, Yao-Wen Chang
Graph-based subfield scheduling for electron-beam photomask fabrication. ISPD (2012)
Shao-Yun Fang, Yao-Wen Chang, Wei-Yu Chen
A novel layout decomposition algorithm for triple patterning lithography. DAC (2012)
Shao-Yun Fang, Yao-Wen Chang
Simultaneous flare level and flare variation minimization with dummification in EUVL. DAC (2012)
Shao-Yun Fang, Tzuo-Fan Chien, Yao-Wen Chang
Redundant-wires-aware ECO timing and mask cost optimization. ICCAD (2010)