Instruction buffering for nested loops in low power design.
Chi Ta WuTingTing HwangPublished in: ISCAS (4) (2002)
Keyphrases
- low power
- power consumption
- low power consumption
- single chip
- high speed
- logic circuits
- low cost
- vlsi architecture
- cmos technology
- digital signal processing
- gate array
- power dissipation
- wireless transmission
- ultra low power
- mixed signal
- vlsi circuits
- nm technology
- design methodology
- power reduction
- low complexity
- design process
- high power