Instruction buffering for nested loops in low-power design.
Chi Ta WuAng-Chih HsiehTingTing HwangPublished in: IEEE Trans. Very Large Scale Integr. Syst. (2006)
Keyphrases
- low power
- single chip
- power consumption
- low cost
- high speed
- low power consumption
- vlsi architecture
- logic circuits
- digital signal processing
- gate array
- power dissipation
- cmos technology
- ultra low power
- mixed signal
- design methodology
- high power
- signal processing
- power reduction
- delay insensitive
- nm technology
- general purpose
- video sequences