Switching-activity driven gate sizing and Vth assignment for low power design.

Yu-Hui Huang Po-Yuan Chen TingTing Hwang

Published in: ASP-DAC (2006)

Keyphrases

low power
cmos technology
power consumption
low cost
single chip
high speed
low power consumption
logic circuits
digital signal processing
gate array
nm technology
power dissipation
vlsi architecture
ultra low power
mixed signal
power reduction
general purpose
real time