Compiler Supports and Optimizations for PAC VLIW DSP Processors.
Yung-Chia LinChung-Lin TangChung-Ju WuMing-Yu HungYi-Ping YouYa-Chiao MooSheng-Yuan ChenJenq Kuen LeePublished in: LCPC (2005)
Keyphrases
- level parallelism
- signal processing
- parallel processing
- digital signal processing
- programming language
- parallel execution
- parallel algorithm
- general purpose
- upper bound
- transactional memory
- digital signal processor
- instruction set
- parallel programming
- pac learning
- high end
- special case
- single processor
- parallel implementation
- multiprocessor systems
- shared memory
- software systems
- theoretical analysis
- verilog hdl