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Apply high-level synthesis design and verification methodology on floating-point unit implementation.
Chia-I Chen
Chin-Yeh Yu
Yen-Ju Lu
Chi-Feng Wu
Published in:
VLSI-DAT (2014)
Keyphrases
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high level synthesis
parallel architecture
design methodology
design space exploration
efficient implementation
pattern recognition
multi agent
higher order
low cost
graphical models
data processing
design space
functional verification