A hardware accelerator for context-based adaptive binary arithmetic decoding in H.264/AVC.
Jian-Wen ChenCheng-Ru ChangYoun-Long LinPublished in: ISCAS (5) (2005)
Keyphrases
- adaptive binary arithmetic coding
- variable length coding
- coding efficiency
- coding scheme
- mpeg avc
- decoding process
- arithmetic coding
- real time
- low cost
- image coding
- hardware and software
- bit rate
- field programmable gate array
- entropy coding
- hardware implementation
- compressed video
- rate distortion
- low complexity
- multiview video coding
- parallel implementation
- source coding
- scalable video coding
- embedded systems
- computer systems
- video sequences