Mely Chen Chi

Publication Activity (10 Years)

Years Active: 1987-2012
Publications (10 Years): 0

Top Topics

Power Reduction

Partitioning Algorithm

Top Venues

Publications

Wen-Pin Tu, Shih-Wei Wu, Shih-Hsu Huang, Mely Chen Chi
NBTI-aware dual threshold voltage assignment for leakage power reduction. ISCAS (2012)
Ho-lin Chang, Hsiang-Cheng Lai, Tsu-Yun Hsueh, Wei-Kai Cheng, Mely Chen Chi
A 3D IC designs partitioning algorithm with power consideration. ISQED (2012)
Tsu-Yun Hsueh, Hsiang-Hui Yang, Wei-Chieh Wu, Mely Chen Chi
A layer prediction method for minimum cost three dimensional integrated circuits. ISQED (2011)
Yu Cheng Hu, Yin Lin Chung, Mely Chen Chi
A multilevel multilayer partitioning algorithm for three dimensional integrated circuits. ISQED (2010)
Jun Cheng Chi, Hung Hsie Lee, Sung Han Tsai, Mely Chen Chi
Gate Level Multiple Supply Voltage Assignment Algorithm for Power Optimization Under Timing Constraint. IEEE Trans. Very Large Scale Integr. Syst. 15 (6) (2007)
Jun Cheng Chi, Tsung Hui Huang, Mely Chen Chi
An IR drop-driven placer for standard cells in a SOC design. SoCC (2005)
Chih-Jen Yen, Wen-Yaw Chung, Mely Chen Chi
A Wide-Swing V_T-Referenced Circuit with Insensitivity to Device Mismatch. VLSI Design (2005)
Chih-Jen Yen, Wen-Yaw Chung, Mely Chen Chi
Micro-power low-offset instrumentation amplifier IC design for biomedical system applications. IEEE Trans. Circuits Syst. I Regul. Pap. (4) (2004)
Chih-Jen Yen, Wen-Yaw Chung, Mely Chen Chi
A Compact Low-Power Buffer Amplifier with Dynamic Bias Control Technique. VLSI Design (2004)
Yu-Hsiung Huang, Mely Chen Chi
Low-power driven standard-cell placement based on a multilevel force-directed algorithm. SoCC (2004)
Chih-Jen Yen, Mely Chen Chi, Wen-Yaw Chung, Shing-Hao Lee
A 0.75-mW analog processor IC for wireless biosignal monitor. ISLPED (2003)
Mely Chen Chi, Shih-Hsu Huang
A Reliable Clock Tree Design Methodology for ASIC Designs. ISQED (2000)
Mely Chen Chi
An Automatic Rectilinear Partitioning Procedure for Standard Cells. DAC (1987)