High-Level Synthesis for Minimum-Area Low-Power Clock Gating.
Shih-Hsu HuangWen-Pin TuBing-Hung LiPublished in: J. Inf. Sci. Eng. (2012)
Keyphrases
- low power
- power consumption
- high level synthesis
- power reduction
- power dissipation
- high speed
- low cost
- low power consumption
- digital signal processing
- energy efficiency
- power saving
- energy saving
- parallel architecture
- logic circuits
- design space exploration
- image sensor
- fine grained
- cmos technology
- graph cuts
- real time