Low-Power Low-Error Fixed-Width Multiplier Design for Digital Signal Processing.
En-Hui ZhangShih-Hsu HuangPublished in: ICCE (2021)
Keyphrases
- digital signal processing
- low power
- power consumption
- low cost
- single chip
- high speed
- power dissipation
- signal processing
- low power consumption
- vlsi architecture
- logic circuits
- cmos technology
- data flow
- gate array
- computer vision and image processing
- image processing
- power reduction
- ultra low power
- efficient implementation
- level set
- pattern recognition
- fixed width
- learning algorithm
- machine learning