Login / Signup
A performance-driven circuit bipartitioning algorithm for multi-FPGA implementation with time-multiplexed I/Os.
Masato Inagi
Yasuhiro Takashima
Yuichi Nakamura
Yoji Kajitani
Published in:
FPT (2006)
Keyphrases
</>
fpga implementation
hardware implementation
learning algorithm
detection algorithm
np hard
dynamic programming
objective function
k means
computational complexity
probabilistic model
software engineering
tree structure
computer vision
graph partitioning
memory efficient
external memory
machine learning