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Performance and reliability driven clock scheduling of sequential logic circuits.
Atsushi Takahashi
Yoji Kajitani
Published in:
ASP-DAC (1997)
Keyphrases
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logic circuits
low power
power consumption
high speed
functional decomposition
scheduling problem
scheduling algorithm
tunnel diode
low cost
gate array
resource allocation
logic synthesis
parallel machines
power dissipation
image analysis
image processing