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Clock Period Minimization of Semi-Synchronous Circuits by Gate-Level Delay Insertion.

Tomoyuki YodaAtsushi TakahashiYoji Kajitani
Published in: ASP-DAC (1999)
Keyphrases
  • high speed
  • higher level
  • power dissipation
  • database
  • data structure
  • low cost
  • power consumption
  • levels of abstraction
  • digital circuits
  • critical path
  • multiple input
  • delay insensitive
  • analog vlsi