Login / Signup
A High-Speed and Low-Power Clock Tree Synthesis by Dynamic Clock Scheduling.
Keiichi Kurokawa
Takuya Yasui
Yoichi Matsumura
Masahiko Toyonaga
Atsushi Takahashi
Published in:
IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (2002)
Keyphrases
</>
high speed
low power
power consumption
single chip
wireless transmission
digital signal processing
high power
low power consumption
frame rate
real time
scheduling problem
vlsi architecture
image sensor
power saving
low cost
b tree
vlsi circuits