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Multi-Clock Cycle Paths and Clock Scheduling for Reducing the Area of Pipelined Circuits.
Bakhtiar Affendi Rosdi
Atsushi Takahashi
Published in:
IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (2006)
Keyphrases
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high speed
power consumption
duty cycle
power reduction
resource allocation
database
scheduling problem
social networks
shortest path
low power
data flow
resource constraints
dynamic scheduling
preventive maintenance
delay insensitive