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A 2-stage-pipelined 16 port SRAM with 590Gbps random access bandwidth and large noise margin.
Koh Johguchi
Yuya Mukuda
Ken-ichi Aoyama
Hans Jürgen Mattausch
Tetsushi Koide
Published in:
IEICE Electron. Express (2007)
Keyphrases
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random access
transmission rate
solid state
memory size
multiview video coding
disk storage
power consumption
allocation scheme
data transmission
signal to noise ratio
flash memory
training set
hard disk
multiresolution
video streaming