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A 0.6-Tbps, 16-port SRAM design with 2-stage- pipeline and multi-stage-sensing scheme.

Koh JohguchiYuya MukudaShinya IzumiHans Jürgen MattauschTetsushi Koide
Published in: ESSCIRC (2007)
Keyphrases
  • multistage
  • single stage
  • stochastic programming
  • lot sizing
  • stochastic optimization
  • power consumption
  • production system
  • optimal control
  • attack detection
  • assembly systems
  • lot streaming