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Architecture and FPGA-Implementation of Scalable Picture Segmentation by 2D Scanning with Flexible Pixel-Block Size.
Tetsushi Koide
R. Kimura
T. Sugahara
K. Okazaki
Hans Jürgen Mattausch
Published in:
ICNC (2010)
Keyphrases
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fpga implementation
block size
hardware implementation
image blocks
pixel wise
quadtree
field programmable gate array
image processing algorithms
image segmentation
test images
bit rate
motion vectors
real time
pixel values
multiscale
binary images
signal processing
transfer function
low cost
image data