Xiangyu Zhang

Publication Activity (10 Years)

Years Active: 2016-2024
Publications (10 Years): 16

Top Topics

Hough Transform

Modular Architecture

Human Activity Recognition

Learning Vector Quantization

Top Venues

IEEE Trans. Circuits Syst. I Regul. Pap.

IEICE Trans. Inf. Syst.

Publications

Hongyu Wang, Xiangyu Zhang, Xin Lou
A Multi-scale Block PatchMatch-based Unified Algorithm for Efficient 6-D Vision Processing. ISCAS (2024)
Kangjie Long, Chaolin Rao, Xiangyu Zhang, Wenbin Ye, Xin Lou
FPGA Accelerator for Human Activity Recognition Based on Radar. IEEE Trans. Circuits Syst. II Express Briefs 71 (3) (2024)
Mengchuan Dong, Wei Zhou, Cong Pang, Xiangyu Zhang, Xin Lou
Image Frequency Separation Residual Network for End-to-end RAW to RGB Mapping. AICAS (2023)
Haoyan Li, Wei Zhou, Xiangyu Zhang, Xin Lou
An Efficient Frequency Domain Vision Pipeline From RAW Images to Backend Tasks. ISCAS (2023)
Xiangyu Zhang, Ling Zhang, Xin Lou
A Raw Image-Based End-to-End Object Detection Accelerator Using HOG Features. IEEE Trans. Circuits Syst. I Regul. Pap. 69 (1) (2022)
Jungang Guan, Fengwei An, Xiangyu Zhang, Lei Chen, Hans Jürgen Mattausch
Energy-Efficient Hardware Implementation of Road-Lane Detection Based on Hough Transform with Parallelized Voting Procedure and Local Maximum Algorithm. IEICE Trans. Inf. Syst. (6) (2019)
Aiwen Luo, Fengwei An, Xiangyu Zhang, Hans Jürgen Mattausch
A Hardware-Efficient Recognition Accelerator Using Haar-Like Feature and SVM Classifier. IEEE Access 7 (2019)
Fengwei An, Xiangyu Zhang, Aiwen Luo, Lei Chen, Hans Jürgen Mattausch
A Hardware Architecture for Cell-Based Feature-Extraction and Classification Using Dual-Feature Space. IEEE Trans. Circuits Syst. Video Technol. 28 (10) (2018)
Aiwen Luo, Fengwei An, Xiangyu Zhang, Lei Chen, Hans Jürgen Mattausch
Resource-Efficient Object-Recognition Coprocessor With Parallel Processing of Multiple Scan Windows in 65-nm CMOS. IEEE Trans. Very Large Scale Integr. Syst. 26 (3) (2018)
Xiangyu Zhang, Fengwei An, Lei Chen, Idaku Ishii, Hans Jürgen Mattausch
A Modular and Reconfigurable Pipeline Architecture for Learning Vector Quantization. IEEE Trans. Circuits Syst. I Regul. Pap. (10) (2018)
Zunkai Huang, Xiangyu Zhang, Lei Chen, Yongxin Zhu, Fengwei An, Hui Wang, Songlin Feng
A Vector-Quantization Compression Circuit With On-Chip Learning Ability for High-Speed Image Sensor. IEEE Access 5 (2017)
Fengwei An, Xiangyu Zhang, Lei Chen, Idaku Ishii
Object-recognition VLSI for pedestrian detection in automotive applications. ASICON (2017)
Jungang Guan, Fengwei An, Xiangyu Zhang, Lei Chen, Hans Jürgen Mattausch
Real-Time Straight-Line Detection for XGA-Size Videos by Hough Transform with Parallelized Voting Procedures. Sensors 17 (2) (2017)
Fengwei An, Xiangyu Zhang, Lei Chen, Hans Jürgen Mattausch
Dynamically reconfigurable system for LVQ-based on-chip learning and recognition. ISCAS (2016)
Yuki Fujita, Fengwei An, Aiwen Luo, Xiangyu Zhang, Lei Chen, Hans Jürgen Mattausch
Pixel-based pipeline hardware architecture for high-performance Haar-like feature extraction. APCCAS (2016)
Fengwei An, Xiangyu Zhang, Lei Chen, Hans Jürgen Mattausch
A Memory-Based Modular Architecture for SOM and LVQ with Dynamic Configuration. IEEE Trans. Multi Scale Comput. Syst. 2 (4) (2016)