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Test cost reduction by at-speed BISR for embedded DRAMs.

Yoshihiro NaguraMichael MullinsAnthony SauvageauYoshinoro FujiwaraKatsuya FurueRyuji OhmuraTatsunori KomoikeTakenori OkitakaTetsushi TanizakiKatsumi DosakaKazutami ArimotoYukiyoshi KodaTetsuo Tada
Published in: ITC (2001)
Keyphrases
  • cost reduction
  • high speed
  • embedded systems
  • real time
  • multistage
  • cost savings
  • reinforcement learning