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Dependable SRAM with enhanced read-/write-margins by fine-grained assist bias control for low-voltage operation.
Koji Nii
Makoto Yabuuchi
Hidehiro Fujiwara
Hirofumi Nakano
Kazuya Ishihara
Hiroyuki Kawai
Kazutami Arimoto
Published in:
SoCC (2010)
Keyphrases
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fine grained
low voltage
read write
coarse grained
random access memory
design considerations
access control
power line
leakage current
cmos technology
massively parallel
real time
power management
database management systems
signal processing
digital images
databases
data lineage