Design and Implementation of a Configurable Heterogeneous Multicore SoC With Nine CPUs and Two Matrix Processors.
Hiroyuki KondoMasami NakajimaNorio MasuiSugako OtaniNaoto OkumuraYukari TakataTakashi NasuHirokazu TakataTakashi HiguchiMamoru SakugawaHayato FujiwaraKazuya IshidaKoichi IshimiSatoshi KanekoTeruyuki ItohMasayuki SatoOsamu YamamotoKazutami ArimotoPublished in: IEEE J. Solid State Circuits (2008)
Keyphrases
- implementation issues
- parallel processing
- efficient implementation
- hardware software co design
- parallel algorithm
- case study
- circuit design
- parallel distributed
- highly parallel
- rapid prototyping
- signal processor
- single chip
- high end
- parallel computation
- current status
- computer architecture
- future development
- design methodology
- hardware implementation