An embedded DRAM with a 143-MHz SRAM interface using a sense-synchronized read/write.
Yasuhiko TaitoTetsushi TanizakiMitsuya KinoshitaFutoshi IgaueTakeshi FujinoKazutami ArimotoPublished in: IEEE J. Solid State Circuits (2003)
Keyphrases
- read write
- embedded dram
- random access memory
- flash memory
- cmos technology
- dynamic random access memory
- low power
- main memory
- high speed
- low voltage
- file system
- database systems
- parallel processing
- design considerations
- power consumption
- data storage
- b tree
- image sensor
- database operations
- random access
- embedded systems
- memory subsystem
- databases