A 312-MHz 16-Mb random-cycle embedded DRAM macro with a power-down data retention mode for mobile applications.
Fukashi MorishitaIsamu HayashiHideto MatsuokaKazuhiro TakahashiKuniyasu ShigetaTakayuki GyohtenMitsutaka NiiroHideyuki NodaMako OkamotoAtsushi HachisukaAtsushi AmoHiroki ShinkawataTatsuo KasaokaKatsumi DosakaKazutami ArimotoKazuyasu FujishimaKenji AnamiTsutomu YoshiharaPublished in: IEEE J. Solid State Circuits (2005)