The Circuits and Robust Design Methodology of the Massively Parallel Processor Based on the Matrix Architecture.
Hideyuki NodaTetsushi TanizakiTakayuki GyohtenKatsumi DosakaMasami NakajimaKatsuya MizumotoKanako YoshidaTakenobu IwaoTetsu NishijimaYoshihiro OkunoKazutami ArimotoPublished in: IEEE J. Solid State Circuits (2007)
Keyphrases
- design methodology
- massively parallel
- chip design
- processing elements
- parallel architectures
- high performance computing
- physical design
- design procedure
- hardware software
- parallel computers
- object oriented
- fine grained
- parallel computing
- fuzzy neural network
- design process
- parallel programming
- floating point unit
- computer architecture
- parallel machines
- power dissipation
- relational databases
- decision making
- database
- hardware design
- formal specification
- parallel processors
- parallel architecture
- mathematical model
- scheduling problem
- expert systems
- cmos technology
- databases