High-performance embedded SOI DRAM architecture for the low-power supply.
Tadaaki YamauchiFukashi MorishitaShigenobu MaedaKazutami ArimotoKazuyasu FujishimaHideyuki OzakiTsutomu YoshiharaPublished in: IEEE J. Solid State Circuits (2000)
Keyphrases
- low power
- cmos technology
- embedded dram
- dynamic random access memory
- silicon on insulator
- high speed
- power consumption
- signal processor
- low cost
- vlsi architecture
- low voltage
- low power consumption
- mixed signal
- single chip
- random access memory
- high power
- parallel processing
- nm technology
- wireless transmission
- image sensor
- gate array
- embedded systems
- vlsi circuits
- power dissipation
- data center
- design considerations
- real time
- power reduction
- design methodology