The Design and Implementation of the Massively Parallel Processor Based on the Matrix Architecture.
Hideyuki NodaMasami NakajimaKatsumi DosakaKiyoshi NakataMotoki HigashidaOsamu YamamotoKatsuya MizumotoTetsushi TanizakiTakayuki GyohtenYoshihiro OkunoHiroyuki KondoYukihiko ShimazuKazutami ArimotoKazunori SaitoToru ShimizuPublished in: IEEE J. Solid State Circuits (2007)
Keyphrases
- massively parallel
- parallel computers
- processing elements
- hardware architecture
- computer architecture
- hardware design
- instruction set
- efficient implementation
- computation intensive
- memory management
- parallel computing
- hardware implementation
- parallel architectures
- fine grained
- fpga device
- linear algebra
- parallel architecture
- graphics processing units
- floating point unit
- xilinx virtex
- optimal solution
- high performance computing
- image processing algorithms
- pairwise