A 40GOPS 250mW massively parallel processor based on matrix architecture.
Masami NakajimaHideyuki NodaKatsumi DosakaKiyoshi NakataMotoki HigashidaOsamu YamamotoKatsuya MizumotoHiroyuki KondoYukihiko ShimazuKazutami ArimotoKazunori SaitohToru ShimizuPublished in: ISSCC (2006)
Keyphrases
- massively parallel
- processing elements
- parallel computers
- parallel architectures
- fine grained
- parallel computing
- floating point unit
- high performance computing
- instruction set
- parallel machines
- parallel architecture
- power consumption
- computer architecture
- mesh connected
- hardware architecture
- distributed memory
- field programmable gate array
- special case
- computing systems
- parallel processing
- bit rate
- data processing