A 5.3-GB/s embedded SDRAM core with slight-boost scheme.
Akira YamazakiTadato YamagataMakoto HatakenakaAtsushi MiyanishiIsao HayashiShigeki TomishimaAtsuo MangyoYoshio YukinariTakashi TatsumiMasashi MatsumuraKazutami ArimotoMichihiro YamadaPublished in: IEEE J. Solid State Circuits (1999)