A 5-MHz, 3.6-mW, 1.4-V SRAM with nonboosted, vertical bipolar bit-line contact memory cell.
Hirotoshi SatoHideaki NagaokaHiroaki HondaYukio MakiTomohisa WadaYutaka AritaKazuhito TsutsumiMakoto TaniguchiMichihiro YamadaPublished in: IEEE J. Solid State Circuits (1998)
Keyphrases
- random access memory
- power consumption
- nm technology
- design considerations
- low voltage
- cmos technology
- low power
- embedded dram
- positive and negative
- power dissipation
- high speed
- clock frequency
- memory access
- memory usage
- main memory
- line segments
- production line
- power supply
- memory management
- hash table
- high density
- memory requirements
- high frequency
- shift register
- hd video
- video coding
- neural network