Hybrid masking using intra-masking dual-rail memory on LUT for SCA-Resistant AES implementation on FPGA (abstract only).
Anh-Tuan HoangTakeshi FujinoPublished in: FPGA (2013)
Keyphrases
- high speed
- human visual system
- empirically derived
- hardware implementation
- hardware architectures
- high level
- image quality
- hardware architecture
- information loss
- hardware design
- memory management
- software implementation
- dedicated hardware
- fpga device
- memory usage
- efficient implementation
- memory requirements
- field programmable gate array
- fpga implementation
- fpga technology
- real time image processing
- parallel architecture
- real time
- computational power
- signal processing
- image processing