Intra-masking dual-rail memory on LUT implementation for tamper-resistant AES on FPGA.
Anh-Tuan HoangTakeshi FujinoPublished in: FPGA (2012)
Keyphrases
- high speed
- hardware implementation
- signal processing
- hardware architectures
- real time
- software implementation
- advanced encryption standard
- memory usage
- hardware architecture
- computational power
- dedicated hardware
- real time image processing
- field programmable gate array
- embedded systems
- efficient implementation
- human visual system
- data acquisition
- low cost