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Efficient DPA-Resistance Verification Method with Smaller Number of Power Traces on AES Cryptographic Circuit.

Hiroki ItoMitsuru ShiozakiAnh-Tuan HoangTakeshi Fujino
Published in: DSD (2012)
Keyphrases
  • verification method
  • small number
  • real time
  • power consumption
  • maximum number
  • neural network
  • genetic algorithm
  • decision trees
  • lightweight
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  • smart card