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Intra-Masking Dual-Rail Memory on LUT Implementation for SCA-Resistant AES on FPGA.
Anh-Tuan Hoang
Takeshi Fujino
Published in:
ACM Trans. Reconfigurable Technol. Syst. (2014)
Keyphrases
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high speed
hardware implementation
memory management
real time
hardware design
hardware architecture
hardware architectures
advanced encryption standard
memory requirements
software implementation
dedicated hardware
reconfigurable hardware
fpga technology