Osamu Nomura

Publication Activity (10 Years)

Years Active: 2003-2024
Publications (10 Years): 5

Top Topics

Fpga Implementation

Boltzmann Machine

Top Venues

IEEE Trans. Circuits Syst. II Express Briefs

IEEE Trans. Ind. Informatics

Publications

Soshi Hirayae, Kanta Yoshioka, Atsuki Yokota, Ichiro Kawashima, Yuichiro Tanaka, Yuichi Katori, Osamu Nomura, Takashi Morie, Hakaru Tamukoh
Enhancing Memory Capacity of Reservoir Computing with Delayed Input and Efficient Hardware Implementation with Shift Registers. ISCAS (2024)
Kanta Yoshioka, Yuichi Katori, Yuichiro Tanaka, Osamu Nomura, Takashi Morie, Hakaru Tamukoh
FPGA Implementation of a Chaotic Boltzmann Machine Annealer. IJCNN (2023)
Ninnart Fuengfusin, Hakaru Tamukoh, Yuichiro Tanaka, Osamu Nomura, Takashi Morie
Efficient Repetition Coding for Deep Learning Towards Implementation Using Emerging Non-Volatile Memory with Write-Errors. IJCNN (2023)
Tao Li, Yitao Ma, Ko Yoshikawa, Osamu Nomura, Tetsuo Endoh
Energy-Efficient Convolution Module With Flexible Bit-Adjustment Method and ADC Multiplier Architecture for Industrial IoT. IEEE Trans. Ind. Informatics 18 (5) (2022)
Osamu Nomura, Yusuke Sakemi, Takeo Hosomi, Takashi Morie
Robustness of Spiking Neural Networks Based on Time-to-First-Spike Encoding Against Adversarial Attacks. IEEE Trans. Circuits Syst. II Express Briefs 69 (9) (2022)
Osamu Nomura, Takashi Morie
Projection-Field-Type VLSI Convolutional Neural Networks Using Merged/Mixed Analog-Digital Approach. ICONIP (1) (2007)
Osamu Nomura, Takashi Morie, Keisuke Korekado, Teppei Nakano, Masakazu Matsugu, Atsushi Iwata
An Image-Filtering LSI Processor Architecture for Face/Object Recognition Using a Sorted Projection-Field Model Based on a Merged/Mixed Analog-Digital Architecture. IEICE Trans. Electron. (6) (2006)
Osamu Nomura, Takashi Morie, Masakazu Matsugu, Atsushi Iwata
A Convolutional Neural Network VLSI Architecture Using Sorting Model for Reducing Multiply-and-Accumulation Operations. ICNC (3) (2005)
Keisuke Korekado, Takashi Morie, Osamu Nomura, Hiroshi Ando, Teppei Nakano, Masakazu Matsugu, Atsushi Iwata
A VLSI convolutional neural network for image recognition using merged/mixed analog-digital architecture. J. Intell. Fuzzy Syst. 15 (3-4) (2004)
Osamu Nomura, Takashi Morie, Keisuke Korekado, Masakazu Matsugu, Atsushi Iwata
A Convolutional Neural Network VLSI Architecture Using Thresholding and Weight Decomposition. KES (2004)
Keisuke Korekado, Takashi Morie, Osamu Nomura, Hiroshi Ando, Teppei Nakano, Masakazu Matsugu, Atsushi Iwata
A Convolutional Neural Network VLSI for Image Recognition Using Merged/Mixed Analog-Digital Architecture. KES (2003)