A 8.8-ns 54 54-Bit Multiplier Using New Redundant Binary Architecture.

Hiroshi Makino Yasunobu Nakase Hirofumi Shinohara

Published in: ICCD (1993)

Keyphrases

logical operations
gray code
management system
hardware implementation
binary representation
real time
associative memory
design considerations
run length
denoising
software architecture
network architecture
floating point
error correcting codes
layered architecture
highly redundant