A low power SRAM using auto-backgate-controlled MT-CMOS.
Koji NiiHiroshi MakinoYoshiki TsujihashiChikayoshi MorishimaYasushi HayakawaHiroyuki NunogamiTakahiko ArakawaHisanori HamanoPublished in: ISLPED (1998)
Keyphrases
- low power
- power consumption
- low cost
- high speed
- single chip
- cmos technology
- machine translation
- wireless transmission
- vlsi architecture
- vlsi circuits
- image sensor
- digital signal processing
- logic circuits
- high power
- low power consumption
- power reduction
- power dissipation
- power management
- mixed signal
- delay insensitive
- ultra low power
- power saving