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A 600-MHz 54×54-bit multiplier with rectangular-styled Wallace tree.

Niichi ItohYuka NaemuraHiroshi MakinoYasunobu NakaseTsutomu YoshiharaYasutaka Horiba
Published in: IEEE J. Solid State Circuits (2001)
Keyphrases
  • tree structure
  • high speed
  • binary tree
  • data sets
  • floating point
  • bit vector
  • b tree
  • tree models
  • neural network
  • decision trees
  • index structure
  • tree structures
  • type ii
  • successive approximation