A low power NoC router using the marching memory through type.
Ryota YasudoTakahiro KagamiHideharu AmanoYasunobu NakaseMasashi WatanabeTsukasa OishiToru ShimizuTadao NakamuraPublished in: COOL Chips (2014)
Keyphrases
- low power
- network on chip
- power dissipation
- power consumption
- high speed
- low cost
- cmos technology
- single chip
- wireless transmission
- logic circuits
- digital signal processing
- vlsi architecture
- high power
- data transfer
- low power consumption
- power reduction
- routing algorithm
- image processing
- delay insensitive
- gate array
- ultra low power