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Takahiro Kagami
Publication Activity (10 Years)
Years Active: 2013-2019
Publications (10 Years): 2
Top Topics
Low Power
Network On Chip
Logic Circuits
Power Saving
Top Venues
NOCS
CLUSTER
COOL Chips
DATE
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Publications
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Hiroaki Imade
,
Takahiro Kagami
,
Tomohiro Otawa
,
Kouichi Hirai
,
Yoshio Sakaguchi
,
Naoyuki Fujita
Automatic Power Saving Method by Energy Aware Job Scheduler.
CLUSTER
(2019)
Takahiro Kagami
,
Hiroki Matsutani
,
Michihiro Koibuchi
,
Yasuhiro Take
,
Tadahiro Kuroda
,
Hideharu Amano
Efficient 3-D Bus Architectures for Inductive-Coupling ThruChip Interfaces.
IEEE Trans. Very Large Scale Integr. Syst.
24 (2) (2016)
Ryota Yasudo
,
Takahiro Kagami
,
Hideharu Amano
,
Yasunobu Nakase
,
Masashi Watanabe
,
Tsukasa Oishi
,
Toru Shimizu
,
Tadao Nakamura
Design of a low power NoC router using Marching Memory Through type.
NOCS
(2014)
Hiroki Matsutani
,
Michihiro Koibuchi
,
Ikki Fujiwara
,
Takahiro Kagami
,
Yasuhiro Take
,
Tadahiro Kuroda
,
Paul Bogdan
,
Radu Marculescu
,
Hideharu Amano
Low-latency wireless 3D NoCs via randomized shortcut chips.
DATE
(2014)
Ryota Yasudo
,
Takahiro Kagami
,
Hideharu Amano
,
Yasunobu Nakase
,
Masashi Watanabe
,
Tsukasa Oishi
,
Toru Shimizu
,
Tadao Nakamura
A low power NoC router using the marching memory through type.
COOL Chips
(2014)
Takahiro Kagami
,
Hiroki Matsutani
,
Michihiro Koibuchi
,
Hideharu Amano
Headfirst sliding routing: A time-based routing scheme for bus-NoC hybrid 3-D architecture.
NOCS
(2013)