Reconfigurable synchronized dataflow processor.
Hiroshi SasakiHitoshi MaruyamaHideaki TsukiokaNobuyoshi ShojiHiroaki KobayashiTadao NakamuraPublished in: ASP-DAC (2000)
Keyphrases
- systolic array
- data flow
- dynamic reconfiguration
- digital signal
- reconfigurable architecture
- low cost
- application specific
- computation intensive
- parallel processing
- high speed
- functional units
- database machine
- parallel computing
- instruction set
- control flow
- general purpose processors
- single chip
- high end
- software systems
- general purpose
- parallel architecture
- single processor
- multi core processors
- fine grain
- field programmable gate array
- hardware implementation
- graph transformation
- heterogeneous computing
- floating point unit
- neural network
- parallel execution
- parallel architectures
- computer architecture
- signal processing