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3D Layout of Spidergon, Flattened Butterfly and Dragonfly on a Chip Stack with Inductive Coupling Through Chip Interface.
Hiroshi Nakahara
Ryota Yasudo
Hiroki Matsutani
Hideharu Amano
Michihiro Koibuchi
Published in:
ISPAN-FCST-ISCC (2017)
Keyphrases
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low cost
high speed
analog vlsi
programmable logic
physical design
high density
single chip
website
solid models
user interface
circuit design
knowledge representation
cmos technology
vlsi implementation
evolvable hardware
modular design
random access memory
database systems
real time
host computer