Kensuke Iizuka

Publication Activity (10 Years)

Years Active: 2019-2024
Publications (10 Years): 22

Top Topics

Parallel Implementations

Hierarchical Clustering

Message Passing Interface

Top Venues

IEICE Trans. Inf. Syst.

CANDAR (Workshops)

Publications

Hideharu Amano, Kensuke Iizuka
Power analysis of an optical interconnected FPGA cluster for roadside units. ICCE (2024)
Kensuke Iizuka, Kohei Ito, Ryota Yasudo, Hideharu Amano
Power Optimized Design Framework for FPGA Clusters. IPSJ Trans. Syst. LSI Des. Methodol. 17 (2024)
M. M. Imdad Ullah, Akram Ben Ahmed, Kazuei Hironaka, Kensuke Iizuka, Hideharu Amano
A Multi-FPGA Implementation of FM-Index Based Genomic Pattern Search. IEICE Trans. Inf. Syst. 106 (11) (2023)
Yasuyu Fukushima, Kensuke Iizuka, Hideharu Amano
Parallel Implementation of CNN on Multi-FPGA Cluster. IEICE Trans. Inf. Syst. 106 (7) (2023)
Takumi Inage, Kensuke Iizuka, Hideharu Amano
Board Allocation Algorithm for the Resource Management System of FiC. MCSoC (2023)
Yasuyu Fukushima, Kensuke Iizuka, Hideharu Amano
Parallel Implementation of Vision Transformer on a Multi-FPGA Cluster. candar (2023)
Kensuke Iizuka, Haruna Takagi, Aika Kamei, Kazuei Hironaka, Hideharu Amano
Power Analysis and Power Modeling of Directly-Connected FPGA Clusters. IEICE Trans. Inf. Syst. 106 (12) (2023)
Tomoki Shimizu, Kohei Ito, Kensuke Iizuka, Kazuei Hironaka, Hideharu Amano
The Implementation of a Hybrid Router and Dynamic Switching Algorithm on a Multi-FPGA System. IEICE Trans. Inf. Syst. (12) (2022)
Aoi Hiruma, Kensuke Iizuka, Hideharu Amano
Toward a training of CNNs on a multi-FPGA system. CANDARW (2022)
Kensuke Iizuka, Haruna Takagi, Aika Kamei, Kazuei Hironaka, Hideharu Amano
Power Analysis of Directly-connected FPGA Clusters. COOL CHIPS (2022)
Kazuei Hironaka, Kensuke Iizuka, Hideharu Amano
A Message Passing Interface Library for High-Level Synthesis on Multi-FPGA Systems. MCSoC (2022)
Tomoki Shimizu, Kohei Ito, Kensuke Iizuka, Kazuei Hironaka, Hideharu Amano
Hybrid Network of Packet Switching and STDM in a Multi-FPGA System. COOL CHIPS (2021)
Yasuyu Fukushima, Kensuke Iizuka, Hideharu Amano
Parallel Implementation of CNN on Multi-FPGA Cluster. MCSoC (2021)
Takumi Inage, Kazuei Hironaka, Kensuke Iizuka, Kohei Ito, Yasuyu Fukushima, Mitaro Namiki, Hideharu Amano
M-KUBOS/PYNQ Cluster for multi-access edge computing. CANDAR (2021)
Kazuei Hironaka, Kensuke Iizuka, Miho Yamakura, Akram Ben Ahmed, Hideharu Amano
Remote Dynamic Reconfiguration of a Multi-FPGA System FiC (Flow-in-Cloud). IEICE Trans. Inf. Syst. (8) (2021)
Kazuei Hironaka, Kensuke Iizuka, Hideharu Amano
Implementing VTA, a tensor accelerator on Flow-in-Cloud. ACIT (2021)
Kohei Ito, Kensuke Iizuka, Kazuei Hironaka, Yao Hu, Michihiro Koibuchi, Hideharu Amano
Improving the Performance of Circuit-Switched Interconnection Network for a Multi-FPGA System. IEICE Trans. Inf. Syst. (12) (2021)
Kensuke Iizuka, Kohei Ito, Kazuei Hironaka, Hideharu Amano
A Method of Partitioning Convolutional Layer to Multiple FPGAs. ISOCC (2020)
Kohei Ito, Kensuke Iizuka, Kazuei Hironaka, Yao Hu, Michihiro Koibuchi, Hideharu Amano
Implementing a Multi-ejection Switch and Making the Use of Multiple Lanes in a Circuit-switched Multi-FPGA System. CANDAR (Workshops) (2020)
Yugo Yamauchi, Akram Ben Ahmed, Kazuei Hironaka, Kensuke Iizuka, Hideharu Amano
Horizontal division of deep learning applications with all-to-all communication on a multi-FPGA system. CANDAR (Workshops) (2020)
Hiroyuki Noda, Manfred Orsztynowicz, Kensuke Iizuka, Takaaki Miyajima, Naoyuki Fujita, Hideharu Amano
An ARM-based heterogeneous FPGA accelerator for Hall thruster simulation. HEART (2019)
Kazuei Hironaka, Kensuke Iizuka, Akram Ben Ahmed, M. M. Imdad Ullah, Yugo Yamauchi, Yuxi Sun, Miho Yamakura, Aoi Hiruma, Hideharu Amano
Demonstration of Flow-in-Cloud: A Multi-FPGA System. FPL (2019)