A 2-clock-cycle Naïve Bayes classifier for dynamic branch prediction in pipelined RISC microprocessors.
Itaru HidaMasayuki IkebeTetsuya AsaiMasato MotomuraPublished in: APCCAS (2016)
Keyphrases
- bayes classifiers
- bayes classifier
- feature selection
- decision trees
- instruction set
- probability of correct classification
- probability density function
- support vector machine
- naive bayes
- incomplete data
- multi class
- naive bayes classifier
- text classification
- feature extraction
- power consumption
- bayesian framework
- computer architecture
- prior knowledge
- learning algorithm