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A Hardware-efficient Weight Sampling Circuit for Bayesian Neural Networks.
Yuki Hirayama
Tetsuya Asai
Masato Motomura
Shinya Takamaeda
Published in:
Int. J. Netw. Comput. (2020)
Keyphrases
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neural network
pattern recognition
low cost
maximum likelihood
bayesian networks
computing systems
circuit design
fuzzy logic
parallel architectures
digital circuits
real time
hardware and software