FPGA-Based Annealing Processor with Time-Division Multiplexing.
Kasho YamamotoMasayuki IkebeTetsuya AsaiMasato MotomuraShinya Takamaeda-YamazakiPublished in: IEICE Trans. Inf. Syst. (2019)
Keyphrases
- simulated annealing
- high speed
- video streams
- application specific
- monte carlo
- instruction set
- video processing
- high end
- hardware software partitioning
- parallel architecture
- hardware implementation
- case study
- parallel processing
- hardware architecture
- memory management
- single processor
- multi core processors
- smart camera
- signal processing
- multiprocessor systems
- processor core
- general purpose